This invention relates to improved methods and apparatus for thermally processing workpieces, more particularly, thermally processing semiconductor wafers for electronic device fabrication.
High temperature processing of semiconductor wafers is essential to modern micro electronic device manufacturing. These processes include chemical vapor deposition (CVD), silicon epitaxy, silicon germanium, and rapid thermal processes (RTP) such as implant annealing, oxidation and diffusion drive-in. These are performed at temperatures ranging from about 400 to 1200 degrees Celsius in multi-wafer batch reactors, mini-wafer batch reactors, or in single wafer rapid thermal reactors. Numerous standard textbooks and references exist that described elevated temperature processing of semiconductor wafers. Some example references include Peter Van Zant, xe2x80x9cMicrochip Fabricationxe2x80x9d 3rd edition, McGraw-Hill, New York, 1987; John L. Vossen and Werner Kern, xe2x80x9cThin Film Processes,xe2x80x9d Academic Press, Orlando, 1978; S. M. Sze, xe2x80x9cVLSI Technology,xe2x80x9d McGraw-Hill, New York, 1988.
As currently practiced, these systems all have serious problems. For example, a typical batch or mini furnace heats about 25 to 200 wafers by radiation from its hot walls. The heating source is usually electrical elements of Ni-Chrome wire arranged into zones for preheat, deposit, and post heat. Each zone is individually profiled and controlled to maintain the desired wafer temperature profile across the length of the zone. However, these furnaces have drawbacks such as the extremely long time at temperature and the long heat up and cool down times associated with loading and unloading the wafers.
An additional problem of furnace systems occurs because the wafer edges are hotter than the wafer center because of the proximity between the wafer edge and the hot wall radiation source. This situation can produce thermal stress in the wafer""s crystal lattice and create dislocations that result in slip or other defects. These types of defects are known to cause yield problems in modern devices if the defect occurs in the circuit. Another problem can occur when the wafers become bowed or warped, rendering them unfit for further processing. Typically, the wafers are loaded into quartz or SiC boats with slots for holding the wafers. The areas around the slots cause uniformity problems during processing. Furthermore, the wafers can be pinched and sustain localized stresses which can also cause slip.
Another problem is that the wafers are all exposed to different times at elevated temperature. The front wafer is in the furnace the longest and the rear wafer the least amount of time. CVD processes are highly sensitive to temperature, and time at elevated temperature can cause wafer-to-wafer uniformity problems.
Today""s devices require line widths of less than one micron, and junction depths as small as 25 angstroms. In addition, 300 mm wafers have a reduced thermal budget cycle, thus the temperature processing time must be reduced to limit lateral and downward dopant diffusion to meet the required thermal budget cycle.
To meet these requirements, the industry has developed different approaches. One is a reduced batch size furnace with increased spacing between the wafers, thus allowing faster load/unload times with better process uniformities on the wafers.
Another technique is the use of RTP systems which process one wafer at a time and typically uses high intensity quartz halogen lamps as a heat source. They can rapidly heat the wafer at up to 150xc2x0 C./sec to temperature ranges from about 400xc2x0 C. to 1200xc2x0 C. RTP cuts the cycle time by an order of magnitude or more, reduces the time at temperature, and eliminates dopant diffusion problems. With the improvement in process uniformities the RTP systems produce, RTP effectively competes with the furnaces.
In a typical RTP system, the lamps are positioned in optical reflectors at a distance outside of a process chamber that is made of clear fused quartz. The clear fused quartz allows most of the lamp energy to pass through the process chamber to heat the wafer and wafer holder. However, the quartz chamber absorbs some of the energy from the lamps as well as radiation from the wafer and holder. The process chamber must be kept cool to prevent unwanted deposits from coating the process chamber walls. A coating on the processing wall interferes with the radiant energy transfer to the wafer; also, the coating can produce unwanted particles that can get onto the wafer. The wafer edges are close to the cooled wall and this can cause slip and process problems. Due to the cold wall requirement, growth rates using silicon gases are limited so as to minimize the deposits on the process chamber walls. For applications using silane, the growth rate is limited to only about 0.2 microns/minute.
Another problem with using lamps is that only a small portion (approximately 30%) of the lamp energy is directed to the region of the wafer location. The portion of the lamp energy is so small because the lamps are positioned at a distance from the wafer. Specifically, the lamps are outside of the chamber and zoned to deliver energy to one area of the wafer. Consequently, temperature uniformity improvements are difficult to achieve. The heating characteristics of the wafer can change drastically for changes as simple as adjusting the lamp power to achieve a desired temperature. Although the lamps are housed in sophisticated reflectors in an attempt to control the radiated energy, these reflectors and the lamp filaments degrade with time and use, causing unwanted temperature changes across the wafer. Furthermore, a radiant heating system requires many lamps (up to 300) to heat a single wafer, and a great deal of power (up to 300 KW). Lamp heated reactors require sophisticated heating and temperature control systems that are problematic.
Wafer temperature measurement and temperature control are critical to process results for thermal processes. Temperature measurement for lamp-heated systems is also very difficult since the temperature sensor may be affected by the incidental radiation from the lamps and the variations from the wafer surface, which change with temperature and if the wafer is patterned. Typically, the temperature is measured only in a few locations and temperature gradients generally are not measured or controlled during processing.
The use of multipoint thermocouple wafers is commonly used to help profile the lamp power output. However, this exposes the reactor to metallic contamination, and since the wafer cannot be rotated using this technique, temperature gradients due to gas flow etc, are not accounted for.
The wafers are typically loaded onto a susceptor that has a pin lift mechanism to raise/lower the wafers. These pins can scratch the backs of the wafers, create particles, and cause local temperature variations at the pin area. This can cause defects in the crystal structure of the silicon wafer and deposition uniformity problems. The particles on the backside of the wafers can contaminate other wafers during the loading/unloading in the wafer handler. In general, 300 mm wafers are relatively thinner than the 200 mm wafers and require many more pin support points, yet the 300 mm backside surface specification calls for a reduction in backside marks.
Standard systems also have problems related to controlling the temperature of the process gases. When gases are introduced into the system the wafer is cooled at the leading edge. This may cause slip and degrade film quality. The industry recognizes this problem. In response, the industry has attempted to reduce the problem by preheating the gases and using slip rings at the outer areas of the wafer. However, the changes that have been made are still unsatisfactory and failed to fully address the problems of thermally processing wafers, particularly large diameter wafers.
Clearly, there are numerous applications requiring reliable and efficient methods and apparatus for thermally processing workpieces such as semiconductor wafers. Unfortunately, typical methods and apparatus for old-style thermal processing have characteristics that are inadequate for some current applications and future applications. There is still a need for semiconductor wafer thermal processing systems to provide improved temperature control for the wafer and the process gases. There is a need for systems that are simple to operate and simple to maintain. There is a need for systems that provide improved particle performance, improved process results, and higher throughput.
This invention seeks to provide methods and apparatus that can overcome deficiencies in known methods and apparatus for thermally processing workpieces such as semiconductor wafers. One aspect of the present invention includes methods and apparatus for thermally processing semiconductor wafers using a hot wall process chamber having an isothermal zone for performing the elevated temperature processing step. The process chamber is contained in a housing for easier gas handling. Heaters for the process chamber are located between the housing and the process chamber. The heaters are configured to produce a highly stable and highly uniform temperature for the isothermal zone. Gas flow over the wafer is controlled to achieve uniform processing results. A further aspect of the invention includes having zones in the process chamber for which the temperature can be independently controlled for each zone so that the temperature of the process gas can be controlled before the gas has reached the wafer and after the gas has passed the wafer.
Another aspect of the invention includes an apparatus having improved components for lifting and rotating the wafer so as to reduce particle generation, simplify wafer loading, and improve wafer processing uniformity.
A still further aspect of the invention includes an apparatus having components that provide energy efficiency during elevated temperature wafer processing. The apparatus also includes components for efficient use of process gas.
It is to be understood that the invention is not limited in its application to the details of construction and to the arrangements of the components set forth in the following description or illustrated in the drawings. The invention is capable of other embodiments and of being practiced and carried out in various ways. Also, it is to be understood that the phraseology and terminology employed herein are for the purpose of description and should not be regarded as limiting.
As such, those skilled in the art will appreciate that the conception, upon which this disclosure is based, may readily be utilized as a basis for the designing of other structures, methods and systems for carrying out aspects of the present invention. It is important, therefore, that the claims be regarded as including such equivalent constructions insofar as they do not depart from the spirit and scope of the present invention.
Further, the purpose of the foregoing abstract is to enable the U.S. Patent and Trademark Office and the public generally, and especially the scientists, engineers and practitioners in the art who are not familiar with patent or legal terms or phraseology, to determine quickly from a cursory inspection the nature and essence of the technical disclosure of the application. The abstract is neither intended to define the invention of the application, which is measured by the claims, nor is it intended to be limiting as to the scope of the invention in any way.
The above and still further features and advantages of the present invention will become apparent upon consideration of the following detailed descriptions of specific embodiments thereof, especially when taken in conjunction with the accompanying drawings.